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When one of the following system clock options, External Crystal/Resonator, External Clock, External Resistor-Capacitor, or Timer 1 Secondary Oscillator stops supplying a clock signal, a PIC MCU device can still function thanks to the Fail-Safe Clock Monitor (FSCM). By changing a bit in a configuration register, the FSCM must be enabled.
The FSCM continually checks for a loss of the system clock signal while using a logic circuit to monitor the system clock. The device will switch to the internal oscillator in response to that loss of signal at a frequency determined by the Internal Oscillator Frequency Select (IRCF) bits in the oscillator control register (OSCCON).
When the system clock fails and the FSCM switches to the internal oscillator, the Oscillator Fail Interrupt Flag (OSFIF) bit in the Peripheral Interrupt register will be set. When this flag bit is enabled, it can also cause an interrupt.
In order to start an error message or error recovery activity, this can be used to alert the main programme that a switch has occurred. The FCSM will revert back to using the system clock for operation once the system clock resumes operation. Since it is not automatically cleared when the system clock is set back to normal, the indicator flag bit must be cleared in software.
The Global Fail-Safe Clock Monitor market accounted for $XX Billion in 2021 and is anticipated to reach $XX Billion by 2030, registering a CAGR of XX% from 2022 to 2030.
An apparatus is one of the disclosure’s embodiments. The device may have a clock monitor circuit, a control circuit, and a fault injection circuit that are designed to analyse a clock source signal. The clock source signal from the clock source may be replaced or modified by the fault injection circuit to produce a modified clock signal, which is then sent to the clock monitor circuit.
A clock corrective action may be issued by the Fail Safe clock monitor circuit if it is determined that the input clock signal indicates a problematic clock source. The Fail Safe clock monitor circuit may be designed to receive an input clock signal. Time correctional action.
When one of the following system clock options, External Crystal/Resonator, External Clock, External Resistor-Capacitor, or Timer 1 Secondary Oscillator stops supplying a clock signal, a PIC MCU device launched by Microchip Developer can still function thanks to the Fail-Safe Clock Monitor (FSCM).
By changing a bit in a configuration register, the FSCM must be enabled. The FSCM continually checks for a loss of the system clock signal while using a logic circuit to monitor the system clock. The device will switch to the internal oscillator in response to that loss of signal at a frequency determined by the Internal Oscillator Frequency Select (IRCF) bits in the oscillator control register (OSCCON).
When the system clock fails and the FSCM switches to the internal oscillator, the Oscillator Fail Interrupt Flag (OSFIF) bit in the Peripheral Interrupt register will be set. When this flag bit is enabled, it can also cause an interruption. In order to start an error message or error recovery activity, this can be used to alert the main program that a switch has occurred.
The FCSM will revert back to using the system clock for operation once the system clock resumes operation. Since it is not automatically cleared when the system clock is set back to normal, the indicator flag bit must be cleared in the software.
A Power-On Reset (POR) and, if enabled, the Power-Up Reset Timer (PWRT) must have occurred before the FCSM will start monitoring when the External Crystal/Resonator is used as the system clock.
The Fail-Safe Clock monitoring is based on the 31 kHz Internal Oscillator (INTOSC). The division by 64 circuit transforms the INTOSC clock signal into a 488 Hz signal with a period of about 2 milliseconds. The sample clock is this 488 Hz signal. The Set input of a latch circuit receives the system clock that is being tracked.
The Q output is pre-set for each pulse. On each sample pulse, the Q output is set and the 488 Hz sample clock is applied to the latch’s Reset pin. The Q and Q outputs will switch back and forth on an appropriate operating system. The foundation for the Fail-Safe Clock monitoring is the 31 kHz Internal Oscillator (INTOSC). A divide-by-64 circuit produces a 488 Hz signal with a period of about 2 milliseconds when the INTOSC clock signal is applied. The sample clock is this signal at 488 Hz.
A latch circuit’s Set input receives the system clock that is being tracked. The Q output is set on every pulse. The Reset pin of the latch receives the 488 Hz sample clock, and the Q output is set on each sample pulse. The Q and Q outputs will alternate in a good operating system.
