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The Si5320 clock multiplier IC creates standard SONET/SDH reference clocks centred at 19, 155, or 622 MHz from six different input clocks ranging from 19 to 622 MHz. It is intended for optical networking line card designs.
The IC includes all the circuitry required to convert between the common SONET/SDH reference clock frequencies and their corresponding 15/14 FEC frequencies for long-haul applications.
The component is provided in a 9 x 9-mm package and is designed to provide a 0.25-ps jitter performance level in OC-192 systems.
The OC-192/STM-64 SONET/SDH Line Card application illustrates how framers, mappers, and SERDES are driven at different standard clock frequencies by the ZL30414’s output clocks.
The six outputs of the ZL30414 can filter jitter and multiply the reference to popular SONET/SDH frequencies. Three distinct clock frequencies are generated by the gadget concurrently.
Designers can support the number of output clocks they need by independently enabling or disabling each of the ZL30414’s output clocks.
The Global SDH clock multiplier market accounted for $XX Billion in 2021 and is anticipated to reach $XX Billion by 2030, registering a CAGR of XX% from 2022 to 2030.
The ZLTM30414 is the first clock multiplier analogue phase locked loop (APLL) in the SONET (synchronous optical network) and SDH (synchronous digital hierarchy) standards to produce six output clocks from a single device with jitter performance that exceeds OC-192 and STM-64 system requirements.
Stringent timing requirements can be met by SONET and SDH networking equipment designers thanks to their exceptional level of integration and performance.
The ZL30414 APLL creates ultra-low jitter clock outputs in accordance with ITU-T and Telcordia jitter generation criteria for SONET/SDH equipment and receives a single reference input at 19.44 MHz.
The ZL30414 doesn’t require extra circuitry because it has several clocks that support CMOS, CML, and LVPECL outputs, which reduces cost, board space, and design.
