Key Findings
- Chiplet optical interconnects provide high-bandwidth, low-latency communication between chiplets in multi-die systems.
- They address signal integrity and power density challenges in traditional electrical interconnects, particularly at data rates exceeding 100 Gbps.
- Adoption is accelerating with the rise of disaggregated architectures in AI/ML accelerators, HPC, and cloud datacenter infrastructure.
- Optical interconnects reduce I/O bottlenecks and enable energy-efficient communication in complex chiplet assemblies.
- Key players include Ayar Labs, Intel, Broadcom, Synopsys, GlobalFoundries, and TSMC.
- The U.S. and Asia-Pacific lead adoption due to strong investment in chiplet-based computing and photonic integration.
- Industry efforts are converging around co-packaged optics (CPO), photonic chiplets, and standards such as UCIe and AIB.
- Market growth is supported by increasing integration of photonic engines and hybrid bonding advancements.
- Research focuses on silicon photonics, CMOS-compatible lasers, and passive alignment techniques for scalability.
- Chiplet optical interconnects are moving from early R&D into pilot production and commercial deployments in AI/ML and cloud compute markets.
Market Overview
The market for chiplet optical interconnects is gaining momentum as chipmakers increasingly adopt chiplet architectures to overcome the limitations of monolithic SoCs. Optical interconnects offer a scalable path to high-performance communication by leveraging the low-loss and high-bandwidth characteristics of photonics. These technologies are particularly valuable in environments where thermal, electrical, and latency constraints challenge the performance of traditional copper interconnects.
Optical chiplet interfaces are being integrated into heterogeneous compute platforms, where CPUs, GPUs, memory, and accelerators are disaggregated across silicon. These interfaces ensure seamless data flow and energy-efficient communication while enabling advanced computing paradigms in edge AI, HPC, and hyperscale data centers. Chiplet optical interconnects are evolving rapidly alongside developments in silicon photonics, co-packaging, and 2.5D/3D integration.
Chiplet Optical Interconnects Market Size and Forecast
The global chiplet optical interconnects market was valued at USD 140 million in 2024 and is expected to reach USD 1.26 billion by 2030, expanding at a robust CAGR of 44.5% during the forecast period.
The projected growth is driven by increasing deployment in AI chips, datacenter processors, and silicon photonics-enabled platforms. Key contributors include progress in integration techniques such as hybrid bonding, advances in CMOS-compatible photonics, and industry-wide support for optical interconnect standards. The market is transitioning from research labs to high-volume production as cloud and edge compute platforms demand higher throughput and power efficiency.
Future Outlook
Over the next five years, chiplet optical interconnects are expected to transition from niche deployments to standard elements of advanced chiplet-based systems.
With the convergence of packaging technologies, standardization efforts like UCIe, and continued advancements in silicon photonics, the market will witness accelerated commercialization. In particular, photonic chiplets are likely to become integral to AI inference and training hardware, where memory bandwidth and latency bottlenecks constrain performance. The emergence of co-packaged optics will complement electrical I/O in future compute platforms, enabling more scalable and efficient architectures. Industry collaboration between foundries, photonics suppliers, and semiconductor leaders will be critical to overcoming integration and cost barriers.
Chiplet Optical Interconnects Market Trends
- Shift Toward Co-Packaged Optics (CPO): There is a growing industry movement toward CPO, where optical engines are co-packaged with switches and processors to minimize interconnect losses and boost bandwidth density. This trend is reducing dependence on long-reach electrical interfaces and enabling highly integrated optical communication for chiplet systems.
- Integration of Photonic Chiplets: Photonic chiplets with integrated modulators, lasers, and waveguides are increasingly being developed to function as modular optical I/O blocks. These chiplets offer design flexibility and can be manufactured independently, allowing rapid scaling and reuse across product lines.
- UCIe and AIB Standardization: The development of Universal Chiplet Interconnect Express (UCIe) and Intel’s Advanced Interface Bus (AIB) is standardizing optical interconnect protocols, easing interoperability challenges and reducing the time-to-market for new chiplet systems.
- Hybrid Bonding and Passive Alignment: Packaging innovations such as sub-micron hybrid bonding and passive optical alignment are becoming essential to reduce assembly complexity and ensure high-precision connectivity between optical and electrical chiplets.
Market Growth Drivers
- Demand for AI and HPC Compute Efficiency: The surge in compute workloads, especially in AI training and inference, necessitates faster and more efficient chip-to-chip communication. Optical interconnects address latency and power efficiency issues, making them ideal for large-scale accelerator architectures.
- Limitations of Traditional Electrical I/O:As bandwidth per mm of I/O increases, copper interconnects face signal integrity, power, and thermal challenges. Optical links overcome these barriers, providing sustainable performance improvements across multiple die interfaces.
- Advancements in Silicon Photonics: Mature fabrication of modulators, photodetectors, and passive optical components on CMOS-compatible platforms enables scalable integration of optical functions in chiplet architectures. These advancements lower the cost and complexity of deploying optical I/O.
- Industry Collaboration and Ecosystem Growth:Cross-industry initiatives involving foundries, EDA tool providers, and packaging companies are fostering a supportive ecosystem for photonic chiplets, ensuring smoother path from R&D to production for chiplet optical interconnect technologies.
Challenges in the Market
- Packaging and Alignment Complexity: Achieving precise alignment between optical components and electrical chiplets is a significant technical challenge. High-performance optical links demand sub-micron precision, which adds complexity and cost to the packaging process.
- Thermal and Power Management:Despite their efficiency, photonic components such as lasers still generate heat. Managing thermal gradients and ensuring consistent performance across chiplets remains a critical concern for large-scale deployments.
- Standardization and Interoperability: While progress is being made, lack of universally adopted standards for optical chiplet interfaces hampers plug-and-play integration and increases development overhead for multi-vendor systems.
- Manufacturing Yield and Scalability:The immature state of photonic chiplet fabrication leads to yield variability. Scaling to high volumes while maintaining performance and cost targets poses a considerable challenge, especially for commercial applications.
Chiplet Optical Interconnects Market Segmentation
By Interconnect Type
- On-Package Optical Interconnects
- Co-Packaged Optics (CPO)
- Board-Level Optical Links
- Silicon Photonic Chiplets
By Application
- AI/ML Accelerators
- High-Performance Computing (HPC)
- Datacenter Processors
- 2.5D/3D ICs
- Edge Compute Devices
- Networking and Switching
By End-User Industry
- Semiconductor Foundries
- Cloud Service Providers
- Integrated Device Manufacturers (IDMs)
- Network Equipment Vendors
- Research and Development Organizations
By Region
- North America
- Asia-Pacific
- Europe
- Rest of the World
Leading Players
- Ayar Labs
- Intel Corporation
- Broadcom Inc.
- GlobalFoundries
- Synopsys Inc.
- Advanced Micro Devices (AMD)
- Taiwan Semiconductor Manufacturing Company (TSMC)
- Luminous Computing
- Rockley Photonics
- Lightmatter Inc.
Recent Developments
- Ayar Labs unveiled a 2 Tbps optical I/O chiplet for AI and HPC deployments with integrated photonics.
- Intel introduced co-packaged optics for next-gen datacenter processors, targeting PCIe and UCIe interfaces.
- Broadcom partnered with hyperscalers to develop silicon photonic engines optimized for AI networking fabrics.
- TSMC added support for photonic chiplet integration in its 3DFabric advanced packaging roadmap.
- Luminous Computing demonstrated on-chip optical interconnects in a prototype neuromorphic AI processor.
