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Computational lithography, also known as computational scaling, is a group of mathematical and algorithmic techniques intended to increase the resolution that may be achieved using photolithography. As the semiconductor industry struggled to adapt to and beyond the 22 nm CMOS fabrication process technology, computational lithography has risen to the fore in photolithography.
The phrase “computational lithography” was first used in 2005[5] by Brion Technology, which is now a division of ASML, to advertise their platform for hardware-accelerated complete chip lithography simulation. Since then, whole chip mask synthesis solutions have been referred to by the phrase in the industry.
The Global Computational lithography market accounted for $XX Billion in 2022 and is anticipated to reach $XX Billion by 2030, registering a CAGR of XX% from 2024 to 2030.
KLA-Tencor launched the first computational lithography tool to address double-patterning issues. For the first time, the new tool enables users to assess current double-patterning methods and cost-effectively investigate potential solutions to lithography difficulties in design, materials, and process development.
As well as single-pass patterning and immersion methods, this novel computational lithography tool is compatible. Due to the sharp increase in lithography complexity and experimentation costs brought on by the development of double-patterning lithography, chipmakers and circuit designers have faced challenges.
One of the most important tools for reducing these expenses is computational lithography. PROLITH 11 is one of the few computational lithography techniques that can enable engineers to investigate a broad variety of design, material, or process conditions in order to address a specific issue without using fab resources.
The small features of sophisticated devices are built using the double-patterning lithography (DPL) technique, which divides the pattern into two interleaved patterns. Due to the need for new photoresist materials and a double mask set for DPL layers, the procedure is now more difficult and expensive.
Engineers can model this intricate system with an unprecedented level of accuracy using PROLITH 11, and they can use the model to optimise the system by examining the effects of small or significant changes to the mask design, photoresist properties, scanner or process parameters, and printed pattern on the model.
Fabs can speed up time to market and reduce the number of processed wafers that are trashed by employing PROLITH 11 instead of time-consuming, expensive trials on product wafers.
