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Best-in-class Compute Express Link (CXL) Type 3 memory controllers, Smart Memory Controllers are created to address the increasing memory bandwidth and capacity requirements of data centre workloads.
The CXL 1.1 and CXL 2.0 specifications are supported by the SMC 2000 series, which uses the CXL.mem sub-protocol for low-latency memory expansion and the CXL.io sub-protocol for administration.
The low-latency SMC 2000 1632G and SMC 2000 832G memory controllers adhere to DDR4 and DDR5 JEDEC standards, are compliant with CXL 1.1 and CXL 2.0 requirements, and enable PCIe 5.0 specification speeds.
With 16 lanes working at 32 GT/s and two channels of DDR4-3200 or DDR5-4800, the SMC 2000 1632G is the industry’s largest capacity controller, resulting in a significant decrease in the number of host CPU or SoC pins required per memory channel.
AI, ML, High-Performance Computing (HPC), and other applications that need more memory channels to give more memory bandwidth and capacity are typical applications for the SMC family. Additionally, the SMC has a ground-breaking low-latency design that enables memory systems to operate nearly as well in terms of bandwidth and latency as equivalent LRDIMM products.
The Global smart memory controller market accounted for $XX Billion in 2021 and is anticipated to reach $XX Billion by 2030, registering a CAGR of XX% from 2022 to 2030.
To give data centres additional flexibility, Microchip Technology Inc. has released its first compute express link (CXL) smart memory controllers.
SK Hynix just a few days ago unveiled its first CXL DDR5 DRAM form factor before introducing the smart memory controllers.
Microprocessors, graphic processors, and system-on-chips can link to either DDR4 or DDR5 memory via CXL interfaces.
The approach decreases the cost of ownership in the data centre and increases memory bandwidth and capacity per core.
Additionally, whereas conventional memory configurations are fixed, the form factor enables data centres to upgrade or alter memory options.
The memory controllers, known as the SMC 2000, are created in accordance with the CXL 1.1 and CXL 2.0 specifications, the DDR4 and DDR5 JEDEC standards, and PCIe 5.0 specification rates.
