By submitting this form, you are agreeing to the Terms of Use and Privacy Policy.
Measuring wafer geometry and procedures for delivering better wafer geometry measurements are described. For semiconductor process control, wafer front side, back side, and flatness measurements are taken into account.
Without the drawbacks of traditional metrology systems, the measurement tools and techniques in accordance with embodiments of the present disclosure are suited for handling various types of wafers, including patterned wafers.
Obtaining a first set of wafer geometry measurements of a wafer before the wafer polishing process, the first set of wafer geometry measurements including: a first front side height measurement, a first backside height measurement, and a first wafer flatness measurement determining the best-flatness condition for the wafer based on the first front side height measurement, the first backside height measurement, and the first wafer flatness measurement obtained prior to the wafer polishing process; and polishing the wafer using the optimised wafer polishing procedure.
Wafer geometry is a general term for measures of a wafer’s form, flatness, and roughness. Wafer geometry metrics include bow, warp, site flatness, nanotopography, and roughness, all of which have an impact on how well semiconductor manufacturing processes work at various stages in the process flow.
Global bare wafer geometry metrology systems market accounted for $XX Billion in 2022 and is anticipated to reach $XX Billion by 2030, registering a CAGR of XX% from 2023 to 2030.
The industry-standard for inline monitoring of wafer shape, stress, and warp during 3D NAND, advanced DRAM, and cutting-edge logic IC manufacturing is KLA’s new PWG5TM patterned wafer geometry system, which was just announced.
To ensure that the PWG5 offers IC manufacturers metrology capacity that supports their success, a team of engineers and scientists created a variety of technologies, including optical subsystems, an advanced computational architecture, and algorithms.
These technical advancements combine to create thorough wafer geometry data that aids fab engineers in understanding their workflows and putting their IC breakthroughs into production.
The PWG5 addresses a crucial need of IC makers by offering the best dynamic range available in the market for wafer warp measurement, providing inline monitoring and control of wafer warp levels as high as 1000 m.
This makes it possible for IC producers to quickly spot process-induced wafer deformation that could harm patterning. Fab engineers use PWG5 wafer shape data to guide decisions that enhance device processing, such as reworking the wafer, implementing process tool modifications, or feeding data to future processes.
